Delay a pushbutton signal in SystemVerilog

SystemVerilog
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2

*In reply to m0rph:*Welcome,

Welcome. This forum is mainly for writing verification code, not design code. But many of the same skills are required.

You can use another counter, or you can change the counter limit when to move to S1.


always @(posedge clk or negedge reset)
	begin 
		if(~reset) // active low 
			begin 
            			state <= S0; 
            			count <= 0;
                                walk <= 1;      
			end
		else 
			case(state) 
            			S0: if(~pushbtn) // active low
				       walk <=0; // active low
				if(count < (walk ? sec5 : sec1))  
					 begin  
                      				state <= S0; 
                      				count <= count + 1;  
					 end 
				else
					 begin 
                      				state <= S1; 
                      				count <= 0;
                                                walk <= 1; 
					 end  
				S1: if...