Hi All ,
I was referring to Functional Coverage chapter from SystemVerilog LRM .
- Syntax 19-2 says the following :
| bins_keyword bin_identifier [ [ [ covergroup_expression ] ] ] = default [ iff ( expression ) ]
| bins_keyword bin_identifier = default sequence [ iff ( expression ) ]
bins_keyword::= bins | illegal_bins | ignore_bins
This means that default and default sequence could be bins / illegal_bins / ignore_bins i.e wildcard bins would be illegal
- However the last statement of Section 19.5 then says ::
It shall be an error for bins designated as ignore_bins to also specify a default or default sequence.
I find (1) and (2) conflicting since ignore_bins are valid for default and default sequence as per (1) whereas it’s illegal as per (2)