Defining ignore_bins for default and default sequence

Hi All ,

I was referring to Functional Coverage chapter from SystemVerilog LRM .

  • Syntax 19-2 says the following :

| bins_keyword bin_identifier [ [ [ covergroup_expression ] ]  ] = default [ iff ( expression )  ]
| bins_keyword bin_identifier = default sequence [ iff ( expression )  ]
bins_keyword::= bins | illegal_bins | ignore_bins

This means that default and default sequence could be bins / illegal_bins / ignore_bins i.e wildcard bins would be illegal

  • However the last statement of Section 19.5 then says ::

It shall be an error for bins designated as ignore_bins to also specify a default or default sequence.

I find (1) and (2) conflicting since ignore_bins are valid for default and default sequence as per (1) whereas it’s illegal as per (2)

In reply to ABD_91:

These is no conflict here. The BNF excerpt in 19-2 represents the minimum syntax requirement so the code can be parsed. However, the LRM needs to define what that syntax represents and can impose semantic restrictions that makes the code illegal.

An analogous situation would be declaring a real variable r, and an event variable e. The BNF allows you to write r = e, but datatype semantics make it illegal.