Defining a class within a systemverilog macro

SystemVerilog
,
1

I am trying to define a class withing a systemverilog macro. The purpose is, I have multiple sequences that have to define the same class but using a different type. Parameterized class to be specific, but I need to have a type specific definition and not declaration.

This is the code:

define TYPE_CLASS( T ) class foo_c extends foo_base#( T ); \ ovm_object_utils( T::foo_c )
function new( string name = “foo_c” );
super.new( name );
endfunction : new \
→ endclass

I will then use this macro in every sequence with T = type of the sequence. foo_base is basically an ovm_object.
I have a similar macro containing a function definition and that works fine.

I am encountering this error: Systemverilog keyword “endclass” is not expected to be used in this context (=>)

What am i missing?

2

If you are getting this error message in the definition of this macro, not in the use of this macro, then the compiler thinks
endclass is not part of the macro. Check for extra characters after the last backslash ‘
</span>’. Also,
T::foo_c probably should just be
foo_c.

3

In reply to dave_59:

Thanks Dave. That was it…there was an extra TAB after the last backslash.