In reply to mlsxdx:
`define is a compiler directive which is described in section 22.5.1 of the SystemVerilog LRM. Section 22.2 of LRM describes how compiler directives only extend from the point where it is processed.
The compile argument +define+ is a tool specific argument with behavior dependent on the tool implementation. In most cases, it is equivalent to adding a `define to the beginning of every file being compiled. You will need to refer to your tool documentation for additional information.
You should also be aware of how tools handle compilation units and how compiler directives may or may not carry over from one file to another.