In reply to dave_59:
Thanks for your response.
So can I use the “repeat(2) @cb” inside the task?
I believe I do need the fork/join_none statement because I am using the DPI interface to call some C code. That is why I am using SystemVerilog to begin with. The C code I am calling will block execution until some asynchronous external event takes place, so I think I need that code running in a separate process/task/thread (?) so that the initialization thread is not blocked.
I was trying to assert the “do_write” signal high for two clock cycles when the asynchronous event takes place so that my VHDL state machine will be guaranteed to see that event and respond appropriately. So I don’t think I really need any synchronous logic in this whole design. I think everything could be combinational, provided I can find some way to assert the “do_write” signal for the right amount of time and then deassert it. Note that this code will be run in different designs with different clock frequencies, so I would rather not make any specific assumptions about what the clock frequency is.
I wish there was some kind of “wait until” statement in SystemVerilog like there is in VHDL, but if there is, I can’t seem to find it. I wonder if I might be better off doing this design in FLI instead of using SystemVerilog at all.
I can post some more code if it would be helpful to explain the problem better.