In reply to rajan passionate:
The SystemVerilog LRM prohibits accessing class properties directly in a concurrent assertion, but you can do it indirectly. The reason for this restriction is that concurrent assertions get synthesized by the compiler into something like a state machine, and the variables used in the Boolean expressions are implicitly sampled.
What you can do is create your own sampling logic that copies the class properties into intermediate static variables, and use those intermediate variables in your concurrent assertions.