Debugging Constraint Failure

SystemVerilog
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1

Hello,
I am trying to understand why the constraint failure in edaplayground is not observed using +define+FIX

I wanted to confirm with SV experts on the following

  1. Unlike subroutines, properties can’t be overridden in extended class.
    Hence class ‘ext_seq’ essentially has 2 properties named ’ max_id’ & ‘unique_id’ ( in absence of +define+FIX )
    When I assign base_h.max_id = 4; I end up assigning the inherited property max_id whereas the 2nd ‘max_id’ within ‘ext_seq’ is at default value of 0
  2. Hence when body() task of ‘ext_seq’ executes, I observe “unique_id == 0” and axid is constrained between[ 0 : ( 0 - 1 ) ] i.e [0 : 5'b11111]
  3. When inline constrain of id == axid; is used there is a conflict within constraint ‘max_id_width’

Please correct me if I missing something

2

Correct. The class variable base_h.* can only refer to members known by class type base_seq.

3

Thanks Dave. One point I would like to add is that randomization failure occurs only when axid is constrained to be within 5’d16 and 5’d31.
If (2) constraints axid to be within 5’d0 and 5’d15 there is no conflict