In reply to verif_learner:
I am used to adding interface signals only for testbench which will give state of testbench at any point in time.
Debugging using display statements is again a manual check. If you need debugging in RTL code, appropriate amount of checkers should do. Or else you want to debug testbench status, above method of using interface makes debugging testbench with waveforms easier.
To design self debugging testbench also come up with check points your testbench could break and write checks (e.g. timeout counters for a event, assert(STATE) at appropriate point to see if testbench/rtl reached certain state, etc.)
To debug a code with `uvm_info is something and to write a debug friendly code is something else, I think!