The “other” signals are control signals on the interface, and they do not need to be captured in the transaction. Only the data content should be modeled in the transaction, with variables that you can generate declared as rand, and variables that are sampled from the interface not declared as rand. It is the responsibility of your driver and monitor to use the control signals in the interface to abide by the protocol and timing.
Since you’re asking specifically if your bare-bones sequence item is OK to model a write, it appears OK to me. The transfer class need not derive from uvm_sequence_item (uvm_object is OK). Fill in the rest such as constraints and methods to work with an object of this, and try it out in simulation.