Creating an array of parameterizable objects to iterate?

SystemVerilog
1

I’m trying to create an array of objects to iterate through of my test bench. It looks something like this
…


  jtag_chain#(CAP_MEMORY_REG_WIDTH ) cap_memory =  new(.ir_ctl(CAP_MEMORY_CTL));
  jtag_chain#(PSM_MEM_REG_WIDTH    ) psm_mem     = new(.ir_ctl(PSM_MEM_CTL   ));
  jtag_chain all_chains[2] = {cap_memory, psm_mem};

initial begin 
   for(int i = 0; i < 2; i = i + 1) begin
       all_chains[i].do_something(); 
   end
end

However, running this in Questa I’m getting a

** Fatal: (vsim-13144) Illegal literal initialization.

Is there a better recommendation to implement this same sort of behavior?

2

Since each specialization of a parameterized class is a unique type, you need to create a common base class

virtual class jtag_chain_base; 
  pure virtual function void do_something();
endclass
class jtag_base #(int WIDTH) extends  jtag_chain_base;
  virtual function void do_something;
    ...
  endfunction
endclass
...
jtag_chain#(CAP_MEMORY_REG_WIDTH ) cap_memory =  new(.ir_ctl(CAP_MEMORY_CTL));
 jtag_chain#(PSM_MEM_REG_WIDTH    ) psm_mem     = new(.ir_ctl(PSM_MEM_CTL   ));
 jtag_chain_base all_chains[2] = {cap_memory, psm_mem};

Note that you will only be able to access virtual methods defined in jtag_chain_base or other members of its super class if you define jtag_chain_base as an extension of another class.

3

Thanks Dave,

This got me past a step