crc__bits is a variable… therefore its value is not known till runtime.
However for the part select operation in Verilog the ranges should be
statically determinable at compile time. Hence crc[crc_bits:1] is not
legal.
crc__bits is a variable… therefore its value is not known till runtime.
However for the part select operation in Verilog the ranges should be
statically determinable at compile time. Hence crc[crc_bits:1] is not
legal.