Covering Multi-Clock delay windows for multiple transaction simultaneously

Coverage
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1

I have a simple req and ack signal used for an arbitration unit.
A single bit signal for the req and one for the ack.
I’ve been asked to write a coverage scenario to ensure we are seeing clock delays between 4 and 20 cycles between reqs and grants.

The challenge is that I can have multiple outstanding reqs.(Otherwise it would be a simple req ##[4:20] grant).

I keep coming coming up with convulated ideas to count clocks and the number of reqs and grants, but it seems like I’m missing a more direct and simple solution.

2

If your grant’s are in order with your request’s, you can use a local variable of a property to record the serial number of a request and match it with the serial number of a grant. Then you can assert that property.

property rg_range;
int req_number;
(req,req_number = req_counter) |-> ##[4:20] grant && (req_number = grant_counter);
endproperty

I did not verify this syntax, but I hope it gives you an idea.

If your grants are not in order, then you will need to explain how they are matched up.