Covergroups inside VHDL code

In reply to chr_sue:

Hello Chris,

Yes at the moment my coverage is within the env, but it does not have enough “coverage” as the most important thing to check are the signals inside the DUT.

Oh that’s great I did not realise about using a different interface using the bind construct


   bind DUT bind_bfm bind_inst (.inputPortOfBindInterface(registro_act));

Where that bind line would be in the top module and where the bind_bfm interface should write the input data to a monitor connected to the coverage class and therefore the coverage class would access to the data with the analysis ports, would not it?

I did have a look at the example that you mentioned above. And thanks to it I “could” guess which the “parameters” (I do not know how are they called) of the construct were.

And now with a 2nd interface I should sync with the “main” interface that is generating the clk in order to send the data to the monitor in the right time, right?

Thanks!!

P.S: Do you know any other source apart from the bind example in the mixedlang folder to learn more about how to use bind? I read the article of Dave Rich: “The Missing Link: The Testbench to DUT Connection” but apart from that I could not find any more information.