Covergroups inside VHDL code

In reply to chr_sue:
Okay, but If I instantiate it in the TOP module, how can the BFM access to the DUT internal signals?


module top;
   import uvm_pkg::*;
   import scrambler_pkg::*;
`include "scrambler_macros.svh"
`include "uvm_macros.svh"


   scrambler_bfm       bfm();
   scrambler DUT (.clk(bfm.clk), .reset(bfm.reset), .d_in(bfm.d_in),
		  .v_in(bfm.v_in), .d_out(bfm.d_out), .v_out(bfm.v_out));

/*The DUT is a single component.
  I'm not sure about the 3rd argument of the construct. I think it should be the coverage class,
  But I'm not sure if a class can have access to bind or has to access through the interface.
*/
   bind DUT scrambler_bfm tb_classes/coverage.svh (.scrambler_reg(registro_act));

/*I guess I have to declare the variable to hold the data binded as well*/
   bit [6:0] scrambler_reg;
/*But even with this I don't know how the coverage class can access to this vector*/

initial begin
   uvm_config_db #(virtual scrambler_bfm)::set(null, "*", "bfm", bfm);
   run_test();
end

endmodule : top

Thanks again Chris. Hope at least this thread also helps other people struggling using the bind construct.