Covergroup instance warning

SystemVerilog
,
5

In reply to mayurkubavat:

This warning should be ok but I didn’t understand actual cause of this warning.

Here is my code

File 1: —

typedef enum {VAL_RD, VALA_RD, LD_RD, CLRI_WR_CCCC, CLRI_WR_OTHER, MISC} TransType;

class wdt_apb_trans extends apb_trans;
rand TransType tr_type;

covergroup apb_extra_cov; // line number 21
    coverpoint tr_type;
endgroup

function new;
    this.apb_extra_cov = new();
endfunction

endclass

file 2 :-- Cover group is sampled in this class

class wdt_irq_seq extends apb_sequence;
`uvm_object_utils(wdt_irq_seq)

function new (string name = “wdt”);
super.new(name);
endfunction

virtual task extra_traffic;
forever begin
wdt_apb_trans tr = new();
tr.apb_extra_cov.sample();
endtask

endclass