Covergroup Inheritance

SystemVerilog
,
2

In reply to Have_A_Doubt:

Your example extends a class type with a second covergroup type; both must be constructed and sampled independently. The original covergroup gc1 was never extended.

The new feature coming in the next revision of the sv LRM allows you to extend the covergroup type as part of the extended class type. Construction and sampling behave virtually similar to the randomize methods so you only have to construct and sample a single covergroup object.

class  Base ;
    bit [2:0]  a ;
    covergroup  gc1 ;
      auto_a: coverpoint a;
    endgroup
    function  new();
        gc1 = new();
    endfunction

 endclass

 class  Ext  extends  Base ;
   bit [1:0] b ; 
   covergroup extends gc1 ;       
     auto_b: coverpoint b ;
     cross auto_a, auto_b;
   endgroup
   function  new();
       super.new();
   endfunction
 endclass

 module  Covergroup_Inheritance_L3 ;

   Ext  ext1 ;
   initial  begin
     ext1 = new() ;
     #2; ext1.b = 1 ;  ext1.gc1.sample();
     #2; ext1.a = 3 ;  ext1.gc1.sample();
   end
 endmodule

This means you can now create a cross between a coverpoint in the base covergroup with a coverpoint in the extended covergroup. You are also allowed to override an existing coverpoint with a new expression or bin structure.