In reply to chr_sue:
Hello Chris,
Thank you for your reply.
I have done what you said, I compiled both VHDL and SystemVerilog with the “+cover” option.
Also added to the vsim command the arguents you mentioned:
vsim -64 -wlfnocollapse +UVM_TESTNAME=random_test_matlab -sv_lib qmw/qmw_sv/questa/qmw_client_64 -voptargs=+acc -assertdebug -displaymsgmode both -coverage -quiet top -c -do “qmw_demo.do”
But still it does not generate neither “.ucdb” file, nor the “.txt” or the html report.
Thank you,
Antonio