Glad that you’re using my book :)
Your requirements are not clear.
have two clocks A and O, and a constant K=5. I want to count first five events/ticks of A (which are randomly arriving) and forbid O from occurring (else violation). After those 5 ticks, O is the exact copy of A. I tried to count 5 ticks of A but every arrival of A triggers a new thread. I tried to use first_match but couldn’t manage to get the results.
Variables used in assertions are checked at clocking events. Are you saying that A and O are clocks, and you’re trying to count 5 clocking events of A (like rising edges)with no clocking event of O during that time? And then you have one clocking event of O?
OR, are you saying that A and O are variables clocked by separate clocks or the same clock?
You need to clarify your requirements. In any case, I have 2 comments:
first_match( rose(A) ##1 A[=4] ) |=> (A && O)[=1:];
bit A, O, clk;
// that should be written as:
ap_AO: assert property(@(posedge clk)
$rose(A) ##1 A[->4] |-> ##[1:$](A && O));
but every arrival of A triggers a new thread. I tried to use first_match but couldn’t manage to get the results.
first_match is used in antecedents because otherwise the assertion can never succeed. This is because all threads of the antecedent must be exercised.
You’re seeking uniqueness in that you don’t want an event from one thread to affect other threads. I wrote the following for a future update of my book (TBD release date)
http://SystemVerilog.us/uniqueness.pdf
That should help in providing a solution for uniqueness.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115