In reply to ben@SystemVerilog.us:
- I have two variables A and O that are related to each other.
- Each clock cycle of clk, the values of A,O are sampled.
- Initially, the O must be 0 else it would be a violation.
- There is no restriction on A, that when it can come.
- When we see the high value on A for the nth time (say 5th time), then thats the momemt when O should also be 1.
- The sampled value of A can possibly be 1 for five consecutive cycles of clk or it can come literally after a gap of 1000s of cycles of clk.
- O will be 1 once in its life time and after that will die away.
- O can’t be 1 while A is 0, any occurrence of O other than the one specified above is a violation.