Count function in constraint

SystemVerilog
7

In reply to dave_59:

Hi Dave ,

For the following Snippet



`ifdef B
rand bit [7:0] length ; 
`endif

rand bit [7:0] Var ;

`ifdef B // "B"uilt in function
constraint One {  length  == $count_ones(Var) ; }  // Both are random
`else
constraint One {   $count_ones(Var) == 4 ; }  // Number of Ones are Fixed
`endif

Irrespective of whether +define+B is used or not I end up getting a constraint Failure .

I went through the LRM but they haven’t mentioned anything regarding Built-In Functions inside Constraints .

I am confused whether its a Simulator limitation ( Even on the New ones ) or is it illegal to write them

Regards,
AGIS