Count function in constraint

SystemVerilog
4

In reply to dave_59:


class Packet;
rand bit [2:0] length;
rand bit [2:0] A ;

function int count_ones ( bit [2:0] w );
for( count_ones = 0; w != 0; w = w >> 1 )
begin
count_ones += w & 1'b1;
end
endfunction
constraint c1 { length == count_ones(A);
		solve A before length; }
endclass

I have modified the above program to this and it is working properly.

Thank you dave and Anudeeep