Converting e struct to SystemVerilog struct

SystemVerilog
1

Hi *

I would like to convert the following struct definitation from e language:

struct my_e_struct {
     number_field : uint(bits:10);
     pointer_to_next_structure: my_e_struct;
};

To SystemVerilog. I tried:

struct {
   logic [9:0] number_field;
   my_sv_struct pointer_to_next_structure;
} my_sv_struct;

The compiler tells me I that my_sv_struct is not a visible datatype in the curent scope.

Thanks for the help!

2

A struct in e can map to either a struct or class in SystemVerilog. Use a class for object-oriented programming features like inheritance and encapsulation as well as dynamic references. Use a struct for compound data structures.

Since you are trying to define a dynamically linked list, use a class:

class my_sv_struct;
   logic [9:0] number_field;
   my_sv_struct pointer_to_next_structure;
endclass