Hello I would like to know if it is possible to control an UVM testbench via a scripting language like python. The design I have to verify will be controlled with Control/Status registers and those registers will be controlled with a python script. Right now I am connecting my UVM environnement t…

It’s possible to control a UVM testbench from anything that has a C interface using SystemVerilog’s DPI. Actually, if you can open up an IPC socket from anything, you can write a C interface that connects to the socket and connect that the SystemVerilog through the DPI. If you can get away without u…

Control a UVM test by a scripting language (python)

UVM

ylahlou December 20, 2013, 10:10am 4

Hello ,
kindly find an example

Regards
Yassine