Constraints error

SystemVerilog
2

In reply to Verif Engg:


Loop through twice, and get the difference of index. 
class Example;
 
 typedef enum {ADD, SUB, MUL, DIV} instruction; 
 
  rand instruction inst_q[];
 
  //constraint c1 {inst_q.size() inside {[7:11]};}
  constraint c1 {
    inst_q.size() == 8 ;
    foreach(inst_q[i]) {
      foreach(inst_q[j]){
        if(i < j){
          if(inst_q[i] == ADD && inst_q[j] == ADD)  j - i == 2 ;
          if(inst_q[i] == SUB && inst_q[j] == SUB)  j - i == 3 ;
          if(inst_q[i] == MUL && inst_q[j] == MUL)  j - i == 4 ;
          if(inst_q[i] == DIV && inst_q[j] == DIV)  j - i == 5 ;
        
        
        }
      
      }
    } 
    
  }
     
 
endclass
 
module TB;
 
  Example E;
  initial begin
    E = new();
    if(!(E.randomize()))
       $display("Randomization failed \n");
    for (int i = 0; i < E.inst_q.size(); i++) begin
      $display("inst_q[%0d] = %p \n", i, E.inst_q[i]);     
    end  
  end  
 
 
endmodule