Constraint

SystemVerilog
,
2

In reply to 100rabhh:

If you mean none of the bits set in the same position should overlap, the following should work:

class A;
  rand bit [31:0] reg_a [24];
  constraint nonoverlapping {
    foreach(reg_a[,j]) reg_a.sum() with (int'(item[j])) == 1;
  }
endclass

module top;
  A a=new;
  initial repeat(10) begin
    assert(a.randomize());
    foreach(a.reg_a[i]) $displayb(a.reg_a[i]);
    $display;
  end
endmodule