Constraint violation by tool for array size 4

SystemVerilog
3

Results are interesting.From edaplayground we I was using Mentor for array_size of 3, it was showing correct but for synopsys vcs it is showing as below:

class a;
  rand int unsigned arr[3] ;//= {4,3,8,1};
    constraint myc {arr.sum == 10;}
 
  endclass
program test;
 
 
  a b;
  initial
  begin 
  int j;
    b = new;
 
    assert(!b.randomize()); //$display("FAIL");
    foreach(b.arr[i])
      $display("Arr[i] = %d ",b.arr[i]);
 
    j=b.arr.sum();
    $display("\nsum %d\n",j);
 
 
  end
 
endprogram

I used above code.

**Chronologic VCS simulator copyright 1991-2019
Contains Synopsys proprietary information.
Compiler version P-2019.06-1; Runtime version P-2019.06-1; Jun 23 09:31 2020
“testbench.sv”, 15: test.unnamed$$_0.unnamed$$_1: started at 0ns failed at 0ns
Offending ‘(!b.randomize())’
Arr[i] = 3423460335
Arr[i] = 1686592622
Arr[i] = 3479881645

sum 10

$finish at simulation time 0
**
as you can see here, assertion is failing. that means randomization is failing,but I don’t know exact reason for that.