Constraint value repetition

SystemVerilog
7

In reply to rag123:


class matrix;
  rand bit [4:0] arr [3][3];
  constraint block_unique {
        foreach   ( arr[i, j] ) {
          foreach ( arr[k, l] ) {
        if ( ! ( i == k && j == l ) ) {
          arr[i][j] != arr[k][l];
        }
      }
    }
  }
 
endclass : matrix
 
module tb;
  matrix m1;
  initial 
    begin
      m1 = new();
      repeat(10)
        begin
          if (!m1.randomize())
            $display("Error");
          $display ("%p",m1.arr);
        end
    end
 
endmodule