Constraint value repetition

SystemVerilog
3

In reply to rag123:

Hi,

I modified your code a bit and seems to be working as you expected


class matrix;
  rand bit [4:0] arr [3][3];
  constraint a_cst
  {
    unique {arr};
  }
    
endclass : matrix

module tb;
  matrix m1;
  initial 
    begin
      m1 = new();
      repeat(10)
        begin
          if (!m1.randomize())
            $display("Error");
          $display ("%p",m1.arr);
        end
    end

endmodule