Constraint to make sure each value gets randomized at least once

SystemVerilog
1

Hi, how can I make sure each value gets randomized for at least once?

bit [1:0] data; 

repeat (6) begin
    assert (std::randomize(data) with {
        // To make sure data gets 0, 1, 2, 3 at least once within 6 times
        // e.g. You get 2, 2, 3, 1, 3, 0
    });
end
2

Here’s an approach I would take:

module top;
  parameter N = 7;
  class A;
    bit [1:0] array_have[] = {0,1,2,3};
    bit [1:0] array_havent[int] = '{0:0,1:1,2:2,3:3};
    rand bit [1:0] data;
    int remaining = N;
    constraint c{ data inside {array_have};
               array_havent.num() == remaining ->
               data inside {array_havent};
              }
    function void post_randomize();
      array_havent.delete(data);
      remaining--;
    endfunction
  endclass
  A a = new;
  initial repeat (N) begin
    assert(a.randomize());
    $display("%03d %p %03d", a.data, a.array_havent, a.remaining);
  end
endmodule
1 Like
3

Hi @dave_59 , is the requirement without using randc or unique construct?

4

Here an approach, not so optimized though:

class abc;
  
  bit[1:0]  data;
  
  task run();
  for(int i =0; i<4; i++) begin 
    std::randomize(data) with {data == i;};
    $display("data =%0p", data);
  end
  
  repeat(2) begin //{
    std::randomize(data);
    $display("data =%0p", data);     
  end//}
  endtask
endclass: abc
    
module tb;
  abc abc_inst;
  
  initial begin 
    abc_inst= new();
    abc_inst.run(); 
    
  end
endmodule: tb
5

6 numbers of 4 possibilities cannot be unique.
Although randc could be used to generate values that meet the constraints, it does not allow all possible solutions like what they gave as an example.