Constraint to generate a number with consecutive 1s followed by atleast the same number of consective 0's

SystemVerilog
1

I am trying to accomplish the below using constraints:

No. of 1s should be followed by atleast same num of 0s.
// example:: 010110011100010, 111100001100100, 011000111000010

Any advice?

2

What have you tried? What works? What doesn’t work? If you post an example on EDA Plaground, others can provide assistance.

3 
class pattern;
  parameter int N = 64;
  bit [N-1:0] data;
  rand int count;
  rand int unsigned zeros[], ones[];
    
  constraint c1 { 
    count inside {[10:20]};
    ones.size()  == count;
    zeros.size() == count;
    zeros.sum() + ones.sum() == N;
  }
  
  constraint c2 {
    foreach(ones[i])  { ones[i]  inside {[1:10]}; }
    foreach(zeros[i]) { zeros[i] inside {[1:10]}; }
    foreach(zeros[i]) { zeros[i] >= ones[i];      }
  }
  
   function void post_randomize();
     int n;
    
     foreach(ones[i]) begin
       repeat(ones[i])  data[N-n++] = 1'b1;
       repeat(zeros[i]) data[N-n++] = 1'b0;
     end
   endfunction
endclass

Output:
0101010101010111111111000000000010101011111110000000101001010100
0100111111111000000000101001010101010110011111110000000100000000
0011110000110011001011111111000000001010000011100011100010101000
0101100000001000000100010100001010101110001010111111100000000000
0100000010100000010110000010101010100000000001011111000001010100