Constraint solver

SystemVerilog
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6 
constraint c_one {(b=0) -> (c=1) ;}

Implication replaces boolean expression.

If want to know it, check SystemVerilog or PSL LRM.
You can download SystemVerilog LRM from IEEE Standards .

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But please can you describe those cases where some random variables must get values before others?

As to manage randomize order, check 18.5 in SystemVerilog LRM.