Constraint Solver

SystemVerilog
,
2

In reply to soumyarayaprolu:


class test_class;
  rand bit mode;
  rand bit [2:0] depth;

  constraint c1 {
               solve mode before depth;
               if(mode == 0) depth inside {1, 2};
                else if(mode == 1) depth inside {3, 4};
                 else depth >0; depth <4;
              }

  constraint c2 {
               mode == 0;
              }

endclass

module test;
  test_class t1;

  initial begin
    t1 = new;
    repeat(5) begin
      t1.randomize;
      $display(" value of mode is ",t1.mode);
      $display(" value of depth is ",t1.depth);
    end
  end

endmodule