Constraint randomization of an array

SystemVerilog
19

Hi Dave,

I want to randomize my variables such that.

rand logic[7:0] d_addr;
rand logic[7:0] mem_data[4];

constraint dest_c {
d_addr inside {mem_data[0], mem_data[1],mem_data[2], mem_data[3]};
}

I get compilation error. Is there a way to express the above intent that is “d_addr” should attain any of the four values in mem_data array?

Thanks,
Abhiman