In reply to gnich:
As i commented in a previous comment, maybe, the problem you have is due to the intern 32bit item value used in systemverilog to perform the sum.
In your case “vf” is a bit variable of 12 bits. Systemverilog “sum”-function uses the intern “item” 32bit variable. The casting in the constraint of “sum” must be done to allow a proper constraint.
Could you try to replace the
vf.sum == 2048;
with
vf.sum with (item+32b'b0) == 2048;
Let me know, if that works.
Best regards,