Constraint Randomization Interview Question

SystemVerilog
10

I tried an alternate solution ::


class c; 
 
  rand bit[31:0] v;  
 
  rand int int1 ;
 
  constraint  LOW_BOUND     {  int1  inside { [ 0 : 22 ] } ; }
 
  constraint ct22 { $countones(v) == ( 32 - 10 ) ; }  
 
  constraint  VAL  {     foreach( v[i] )  //  Iterates  from  31  to  0 .
                        {   
                             if( i == int1 ) 
                         {  v[ i+:10 ] ==  10'h0 ;  }  //  Issue  here , not  sure  why      
                        }
                   }
 
endclass 
 
module m; 
    c c1=new(); 
 
  initial begin 
    repeat(5) begin
      if (! c1.randomize() ) $display("  Randomization fails ");
      $display("c1.v= %b", c1.v);
 
    end
  end
endmodule  

//  When  Max( int1 )  is  22 , v[ 22 +: 10 ]  == 10'h0  i.e  v[ 31:22 ] == 10'h0 ;

//  When  Min( int1 )  is  0 , v[ 0 +: 10 ]  == 10'h0  i.e  v[ 9:0 ] == 10'h0 ;

This throws Randomization Failure on some Simulators while it works on others .

Any suggestions ?