In reply to UVM_LOVE:
If you want to make the constraints more constricting, you can add them to the with constraint
virtual task body();
...
'uvm_do_on_with (simplewrite, p_sequencer, {
addressspace == 'h00;
address == 'h00;
length inside {[1:5]};
})
...
endclass
Note there is no need to prefix all the variables with ‘simplewrite.’
But if you want to override with conflicting constraints, like length==256, you could either use soft constraints in the class mastersimplewrite, or you could use the factory to override the mastersimplewrite that provides an override for the constraint read_c.