Constraint on array to get even distribution

SystemVerilog
, ,
2

In reply to mlsxdx:

2 ways to have hard distribution.



     typedef enum bit[1:0] {EE0=0, EE1, EE2, EE3} ee_e;

     // 1st method : simple way for your case
     EEs.sum with(int'(item==EE0)) == EEs.size/4;
     EEs.sum with(int'(item==EE1)) == EEs.size/4;
     EEs.sum with(int'(item==EE2)) == EEs.size/4;
     
     // 2nd method : to support more enum type if need
     rand ee_e EEs[];
     rand ee_e helper[4]; 

     foreach(helper[i]) {
       helper[i] == i;
       EEs.sum with(int'(item==helper[i])) == EEs.size/4;
     }