Constraint number generated with bits control

SystemVerilog
3 
class A;
  rand bit[4:0] addr;  
 constraint addr_c {
   $countones(addr ^ const'(addr)) == 3;
 }
endclass
module abc;
  A a1;
  
  initial begin
    for(int i=0;i<10;i++) begin
      a1=new();
      if(!a1.randomize())
        $error("randomization failed");
      $display("%b",a1.addr);
    end
  end
endmodule

I tried the above code but I got output as below:

# vsim -voptargs=+acc=npr
# run -all
# 10011
# 10011
# 11001
# 01110
# 11001
# 10110
# 01101
# 10011
# 10011
# 10110
# exit

here first 2 numbers are same. Am I missing something?