Constraint issue

SystemVerilog
,
1

I don’t have a code. I am new to system verilog … Want to know about constraint. are following conditions possible
and its urgent

class controller;
rand int a;
rand int b;
endclass

following are the constraints
(1) a>10

(2) 10 < b < 20
(3) when a>20 then b>15

Please help me for this I am new to systemverilog . Trying for past 4 hours. I want to write source code for the above conditons

2

In reply to aviation:

Are you in the middle of an interview or test?

class controller;
  rand int a;
  rand int b;
  constraint c1 {a > 10;}
  constraint c2 {10 < b; b < 20;}
  constraint c3 { if (a > 20) b > 15;}
endclass
3

In reply to dave_59:

thank you
yeah

4

In reply to aviation:

At least you are honest about your cheating!