Constraint for two dimensional array

SystemVerilog
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8

In reply to Shashank Gurijala:

Diagonal should follow like below from right to left
1 3 1 6
1 4 6 1
1 6 4 3
6 1 1 3

whole output should be

1 2 3 4 6
2 3 4 6 1
2 4 6 3 2
1 6 5 4 3
6 4 3 2 1
Note:

  1. diagonal matrix left side values should be increment from starting
  2. diagonal matrix right side should be decrement value from diagonal
    Ex: row=3 or i=2
    2 and 4 incremented before 6
    3 and 2 decremented after 6