In reply to dave_59:
ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
constraint sum_product_c {dataq1.sum(q1) with (int’(q1)*int’(dataq2[q1.index])) < 100000; }
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ncelab: *E,CUVUNF (./testbench.sv,25|77): Hierarchical name component lookup failed at ‘index’.