Constraint for sum of products

SystemVerilog
,
5

In reply to rgarcia07:

Dave,
I modified the code as follows and still an error:
// Code your testbench here
// or browse Examples

  class c;
    rand logic [7:0] dataq1 [];
    rand logic [7:0] dataq2 [];
    constraint data_size {dataq1.size() == 10; dataq2.size() == 10; }
    constraint data_items { foreach(dataq1[i]) 
                                dataq1[i] < 100;
                            foreach(dataq2[i])
                                dataq2[i] < 50; }
    constraint sum_c { dataq1.sum() < 10000; dataq2.sum() < 10000; }
    /*constraint sum_product_c {sum_pro() < 500000; }
 
    function longint sum_pro();
      sum_pro = 0;
      foreach(dataq1[i])
        sum_pro += dataq1[i] * dataq2[i]; 
    endfunction 
 */
    constraint sum_product_c {dataq1.sum(dataq1) with (int'(dataq1)*int'(dataq2(q1.index))) < 100000; }
    
  endclass

module tb;

 
  initial
    begin
      c c1;
      c c2;
      c1 = new;
      c2 = new;
      
      void'(c1.randomize());
      void'(c2.randomize());
      
      foreach(c1.dataq1[i])
        $display("%0d  %0d", c1.dataq1[i], c1.dataq2[i]);
      
      foreach(c1.dataq1[i])
        $display("%0d  %0d", c1.dataq1[i], c1.dataq2[i]);
    end
 
 
endmodule