Constraint for randomly distributed 0 and 1

SystemVerilog
1

wanted to write constraint on an array having 1000 number all the number should be either 0 or 1 and with number of ones should be 7 in count which are randomly distributed and rest 993 number are 0
eg:: 000001000000000100101000010100000000010000000000000all zeroes like this

2 
rand bit [999:0] value;
constraint seven_ones { $countones(value) == 7 ; }
1 Like
3

thanks dave for quick solution

class constrain_ex;
   rand bit [999:0] value;
constraint seven_ones { $countones(value) == 7 ; }
   function print();
    
       $write("%0b", value);
     $write("\n");
  endfunction
 endclass
module tb;
  constrain_ex pkt =new();
  initial begin
    pkt.randomize();
    pkt.print();
  end
endmodule

this is the piece of code for reference

4

Please format your code making your code easier for others to read. I have done that for you.

1 Like