Constraint for random Memory access

SystemVerilog
3

The bug here is as follows : (using example values)

First attempt. : addr = 1234, w_r = 0, q = {1234}, sz = 1, idx = 0,
Second attempt : addr = 5678, w_r = 1, q = {1234, 5678}, sz = 2, idx = either 0 or 1

Because your idx can be 0 or 1, you are not quaranteeing that it is indeed address that has already been written into.

I would simplify the code to the below :


class mem;
  rand int addr;
  rand bit w_r; //w_r=0 write 
  int write_addr_q[$];
  
  constraint w_r_cons {(write_addr_q.size()==0) -> (w_r == 0) ;};
  constraint read_addr_cons { (w_r == 1)  -> (addr inside {write_addr_q}); } ;
 
              
  function void post_randomize();
    if(w_r == 0) write_addr_q.push_back(addr);
  endfunction
  
endclass

Note : running this on edaplayground’s ncsim gave me all w_r = 0. But vcs gave me both 0’s and 1’s.