Constraint for multidimensional array

SystemVerilog
,
3

In reply to megamind:

I guess the more simpler code would be this



module test();
  
  class cls;
    rand bit [15:0]md_array[4][4];
  
    constraint c1{ 
      foreach(md_array[i,j]) {
        if(i>j)
          md_array[i][j]==16'h1111;
        else 
          md_array[i][j]==16'h000;
        
      }
     
      
    }
  
  endclass

cls obj;
  initial begin
    obj =new();
    obj.randomize();
    $display("obj.arr = %p",obj.md_array);
    
    
  end
    
endmodule