Constraint for AHB addr phase

SystemVerilog
1

Hi team, I was developing AHB master, i’m facing an issue with pipeline nature of AHB.
my address phase is taking 3 clk cycle. Can i generate a constraint such that my addr changes every posedge of clock?

Thank you.

2

Constraints are used to specify data in a sequence_item. This item does not know anything about clock cycles. Clock timing is used in the driver. Ther you do not need any constraint, because you can retrieve a new seq_item with a new addr after 3 clock cyles.