Constraint for a random variables

SystemVerilog
, , ,
2

This works.

class random2;
rand bit[7:0]a,b;

//constraint a_con{a==b;}
  constraint b_con{(a==b) dist {1:=10,0:=90};
}

function void display();
$display("a=%d,b=%d",a,b);
endfunction

endclass

module ex;
random2 a_h;
initial begin
a_h=new();
repeat(200)
begin
a_h.randomize();
a_h.display();
end
end
endmodule