Constraint for 4KB aligned address - Can not use % operator

SystemVerilog
1

I need to write a sv Constraint for 4KB aligned address without using % operator. is my approach correct?

class ab;
  
  rand bit [15:0] start_addr; 
  
  constraint c1 {start_addr inside {[0:16'hfff]};}
  constraint c2 {start_addr [1:0] == 0;}
  
endclass

module cd;
  ab ab_i;
  initial begin
    ab_i = new();
    repeat (5) begin
    ab_i.randomize();
    $display("value of start_addr %h",ab_i.start_addr);
    end
  end
endmodule
2

Tell us what the correct behavior should be, and then we can tell you if your approach gives you the correct behavior.

3

Hi Dave,

I am trying to learn memory constraints, and this is an practice example I got online. I am still trying to understand the ques, as nothing else is mentioned there are 2 diff understanding of this ques

  1. The address should be 4KB. so max it can be FFFF. and it should be divisible by 4.

  2. The address should be 4kB aligned. it should be divisible by 4KB. hence start_addr [11:0] == 0.

4

Some missing pieces of information in the question.

How many bytes does each address access? If we know this is part of a standard system, we can assume 1 8-bit byte. “Trust, but Verify” should be everyone motto.

Although it may not adversely affect the answer to this question, there’s nothing that tells us the maximum size of the memory being addressed. You assumed a 16-bit address space. It could be 32-bits.

You probably had a typo when you wrote constraint c2 {start_addr [1:0] == 0;} and meant to write start_addr [11:0] == 0;. And there is no need for c1 as the only value that satifies both c1 and c2 is 0.

1 Like