Constraint a variable so that it's less likely to retain its current value

SystemVerilog
8

In reply to dave_59:

In the example below addr picks the values 20 , 71,110 based on the distributions


class packet;
  rand bit [3:0] addr;
 
  constraint addr_range { addr dist { 20 := 5, 71 := 8, 110 := 12 }; }
endclass

I am trying to understand the example in this thread as we are comparing
LHS and RHS(old value) and use dist {1:=5,0:=95};

so what does that mean? it seems like a disconnection w.r.t the example i posted as normally we just have a variable and it picks from the values mentioned after dist based on the distribution

LHS == RHS is the expression and the expression being true (1) has a probability of 5% and the expression being false (0) has 95% probability
{ LHS == RHS) dist {1:=5,0:=95}; }

is my understanding correct? I haven’t seen such an example yet as most examples just talk about variables but seems like we could do the same for conditional expressions