Constraining dynamic packed arrays in a typedef struct

SystemVerilog
1

I am creating a dynamic array of a packed array contained in a struct. The struct is maintained in a package.

The struct is defined like so:

  typedef struct {
    rand real test_data[7:0];
  } t_test_data;

The dynamic array of the struct is created and constrained in a uvm_sequence_item like so:

  rand t_test_data test_data[];
  constraint test_data_c {
    foreach (test_data[i].test_data) {
      test_data[i].test_data inside {[MIN:MAX]};
    }
  }

But unfortunately, this will cause a compilation error:

# ** Error: ** while parsing file included at agent_pkg.sv(38)
# ** at agent_seq_item.sv(60): At least one loop variable declaration is required.
# ** Error: ** while parsing file included at agent_pkg.sv(38)
# ** at agent_seq_item.sv(61): (vlog-2730) Undefined variable: 'i'.

what is the proper syntax to constrain dynamic packed arrays of real data types?

2

Nothing is packed in the code shown. The declaration you show is an dynamic unpacked array of an unpacked struct with a member whose type is an unpacked array of reals.

You need to nest the foreach iterators

 constraint test_data_c {
    foreach (test_data[i]) 
      foreach(test_data[i].test_data[j]) {
        test_data[i].test_data[j] inside {[MIN:MAX]};
    }
  }
3

I corrected the constraint to use nested foreach iterators, and this has resolved the compile time error.

Thank you for the help, it is very much appreciated!

4

As a follow up to the initial question, I am attempting to assign t_test_data.test_data to the 16-bit std_logic_vector port in DUT.

The assignment in the testbench is like so:

initial assign u_test.i_rx_data = '{logic'{tb_vif.i_rx_data.test_data}, logic'{tb_vif.i_rx_data.test_data}};

The interface uses the struct:

t_test_data i_rx_data;

But the signal assignment is generating an error during simulation:

# ** Error: (vsim-8220) This or another usage of 'u_test.i_rx_data' inconsistent with 'VHDL INPUT PORT' object.
#    Time: 0 ps  Iteration: 0  Instance: /tb_top File: tb_top.sv Line: 87
# ** Error (suppressible): (vsim-13215) Cannot assign an unpacked type 'real$[0:7]' to a packed type 'reg'.
#    Time: 0 ps  Iteration: 0  Instance: /tb_top File: tb_top.sv Line: 87
# ** Error (suppressible): (vsim-13215) Cannot assign an unpacked type 'real$[0:7]' to a packed type 'reg'.
#    Time: 0 ps  Iteration: 0  Instance: /tb_top File: tb_top.sv Line: 87